16bit counter

/* 16 bit counter */
module counter (clk, reset, count);
    input clk, reset;
    output [14:0] count;
    reg [14:0] count;
    always @(negedge clk or posedge reset )
         if (reset) 
              count <= 4'b0000;
         else
               count <= count + 1'b1;
endmodule // counter



module TEST;
   reg clk;
   reg reset;
   wire [14:0] count;

   counter one(clk, reset, count);
   always #10 clk <= ~clk; 
 
   initial begin
      clk   = 0;
      reset = 1;
      $monitor( "%t: %b%b", $time,  count, clk);
      #1   reset = 0;
      #2560 $finish;
   end
endmodule