module counter (clk, reset, count);
    input clk, reset;
    output [3:0] count;
    reg [3:0] count;
    always @(posedge clk or posedge reset )
         if (reset) 
              count <= 4'b0000;
         else
               count <= count + 1'b1;
endmodule // counter



module TEST;
   reg clk;
   reg reset;
   wire [3:0] count;

   counter one(clk, reset, count);
   always #5 clk <= ~clk; 
 
   initial begin
      clk   = 0;
      reset = 1;
      $monitor( "%t: %b  %b", $time,  clk, count);
      #1   reset = 0;
      #160 $finish;
   end
endmodule

modena@makoto 22:00:27/140512(..verilog/binary_counter)% ./4bit-counter 0: 0 0000 5: 1 0001 10: 0 0001 15: 1 0010 20: 0 0010 25: 1 0011 30: 0 0011 35: 1 0100 40: 0 0100 45: 1 0101 50: 0 0101 55: 1 0110 60: 0 0110 65: 1 0111 70: 0 0111 75: 1 1000 80: 0 1000 85: 1 1001 90: 0 1001 95: 1 1010 100: 0 1010 105: 1 1011 110: 0 1011 115: 1 1100 120: 0 1100 125: 1 1101 130: 0 1101 135: 1 1110 140: 0 1110 145: 1 1111 150: 0 1111 155: 1 0000 160: 0 0000 modena@makoto 22:00:34/140512(..verilog/binary_counter)%